1. Field of the Invention
This invention relates in general to a data processor and more particularly to obtaining translation information of a data processor.
2. Description of the Related Art
In some data processing systems, address translation to convert a virtual memory or I/O address to a physical memory or alternate I/O address is performed with a remapping function that accesses translation information stored e.g. in a translation lookaside buffer of a memory management unit (MMU) of a data processor.
Debugging processes are utilized e.g. in the development of code for a data processing system. Debugging processes may be implemented with an external debugger, utilizing a debug communication protocol to communicate debug information to the debugger from the data processing system. Providing debug information in real-time, without intrusion on the normal operation of the data processing system is highly desirable, in order for the actual debug operations to remain transparent to operation of the system. One example of a debug communications protocol is the IEEE ISTO-5001 NEXUS debug standard which is used by a debugger operably coupled to the data processor undergoing debug.
Many debug capabilities are defined in ISTO-5001 standard to monitor program execution by providing visibility into program flow and data flow. This visibility consists of a sequence of information messages provided over a dedicated multi-bit or multi-terminal serial interface or auxiliary port to an external development system. Program flow messages are then combined with a static image of the program to reconstruct the actual instruction execution sequence of the embedded processor. Data flow messages track processor reads and writes to pre-defined address ranges.
ISTO-5001 dynamic debug is implemented using program trace messaging including synchronization messaging, and data trace messaging. Implementation of program trace messaging requires monitoring the sequence of instruction fetches performed by the processor core in conjunction with status information which indicates change of flow (COF) events, including direct or indirect change of flow events. Direct COF events involve program counter relative branches and indirect COF events involve register indirect branches and exception vectoring. Implementation of program trace synchronization messages requires the currently executing instruction address or reasonable neighboring instruction address to be transmitted. Implementation of data trace messaging requires monitoring data access addresses and conditionally providing associated data. Data trace messaging includes read messaging or data reads within one or more defined address ranges and write messaging or data writes within one or more defined address ranges.
As part of the operation of the standard, debug messages are generated by the data processor system which contain address and data information for either program events (Program Trace Messaging), or data events (Data Read Messaging, Data Write Messaging), as well as other debug information. This address and data information is typically formatted by the debugger and presented to the user of the debugger. Correlation of the information to the program undergoing execution is an important part of the debugging process, so that actual program flow and the dynamic values of system data variables can be monitored.
In systems employing virtual memory, the user's program and data values may be placed in physical memory address locations which do not correlate with the address locations resulting from the display of the compiled or assembly program and data layout, which correspond to virtual address locations. Virtual to physical address mapping (or translation) is performed by the data processor to obtain the correct program instructions and data variable values.
However, in some embodiments, the virtual to physical mapping information is not known to an external debugger. What is needed is an improved system for providing translation information to external debugger without impacting the operation of a processor core of a data processing system.
The use of the same reference symbols in different drawings indicates identical items unless otherwise noted.